The need for high performance, high capacity information technology systems is driven by several factors. In many industries, critical information technology applications require outstanding levels of service. At the same time, the world is experiencing an information explosion as more and more users demand timely access to a huge and steadily growing mass of data including high quality multimedia content. The users also demand that information technology solutions protect data and perform under harsh conditions with minimal data loss. And computing systems of all types are not only accommodating more data but are also becoming more and more interconnected, raising the amounts of data exchanged at a geometric rate.
Thus, today's data storage systems are used in computing environments for generating and storing large amounts of critical data. Some storage systems support many (e.g., hundreds) of disk drives. Because disk drives are mechanical devices, they have higher peak power requirements than the other electronic devices in the system. In today's market it is important that the power subsystem portion of a storage system supports the maximum and peak power requirements of the system without excessive expense.
A typical disk drive consists of circuit board logic and a Head and Disc Assembly (HDA). The HDA portion of the disk drive includes the spindles platters, head arm and motor that make up the mechanical portion of the disk drive. When power is applied to the disk drive, the circuit board logic powers up and the HDA spins up. During spin up, the HDA requires a higher current than when it is in steady state, i.e., already spun up. This higher current is typically more than two times the steady state current. Therefore, if a storage system attempts to spin up many drives in the system at the same time, the system is required to support a peak power level that is much greater than the maximum power required to operate at steady state.
The more disk drives the system supports, the greater the peak power requirement. It is too expensive to provide a power subsystem that can support enough peak power to spin up many disk drives at once, especially when the excess power is not otherwise needed.
Some types of disk drives offer a separate HDA power input but no built in control over the timing of the application of power to the HDA. Some other types offer limited control. For example, Fibre Channel (“FC”) disk drives compliant with the SFF-8045 rev. 4.7 standard (“SFF-8045” or “8045”) allow the timing of HDA spin up to be controlled via two signal pins, Start—1 and Start—2, that allow the HDA to spin up based on three different conditions. Depending on the state of the Start—1 and Start—2 signals, the disk drive HDA will start drawing current either 1) immediately; 2) after it receives its first SCSI command, or 3) based on its arbitrated loop physical address (ALPA). This provides limited means to stagger the timing of spin up amongst all the drives such that system peak power requirements can be minimized. However, it is difficult for system software to use SCSI commands to control drive spin up timing, because insert and power control signals from the drives are asserted much faster than software can respond.
The ALPA address method is also disadvantageous in at least some circumstances. Consider a storage system capable of supporting 48 disk drives. If a user plugs a single disk drive into the 48th slot in a system in which the other drives are all already at steady state, there is no power-related reason why the drive should not spin up immediately. But because its spin up timing depends on its ALPA address, it will nonetheless take several minutes to spin up.
SFF-8045 describes a POWER_CONTROL (also known as “power control”, “Pwr_control”, “Pwr_ctrl”, or “P_ctl”) signal driven to the drive to control 5V and 12V power switches located on the drive. When this signal is asserted, high, 5V and 12V supplies are applied to the drive circuitry. When this signal is negated, low, 5V and 12V supplies are not connected to the drive circuitry, so that the drive circuitry is powered down. As described in SFF-8045, the drive provides a 10 KOhm pull up resistor from this signal to the 5V input to the drive.
An SFF-8045 compliant drive also has Enable Bypass signals −ENBL BYP CH1 and −ENBL BYP CH2 that control Port Bypass Circuits (PBC) located external to the drive. The PBC allows an FC loop to remain functional in the event of a drive failure or removal. Signal −ENBL BYP CH1 controls the PBC for FC channel 1, and signal −ENBL BYP CH2 controls the PBC for FC channel 2. When these Enable Bypass signals are asserted (low), the PBC bypasses the drive on the associated channel. The Enable Bypass signals remain passively enabled during the hot plugging process and remain enabled until the drive has performed appropriate internal initialization.
Further in accordance with SFF-8045, a −DRIVE PRESENT signal (“drive insert” or “drive inserted” signal) is connected to the drive's ground plane. In an enclosure receiving the drive, a backplane can optionally use the signal to passively detect the presence of the drive by using a detection circuit connected to a tie up resistor. When the drive is not installed, the detection circuit can detect the signal provided through the tie up resistor. When the drive is installed, the signal is grounded through the drive's ground signal and the grounded state can be detected by the detection circuit.
When insertion of one or more new drives is thereby detected, the storage system needs to attempt to spin up the drive or drives in compliance with the power constraints of the system.